1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, a reference voltage circuit having small output voltage fluctuations in response to power supply voltage fluctuations, which is capable of operating at lower voltage and with lower current consumption.
2. Description of the Related Art
In order to improve a power supply rejection ratio of an analog circuit, a method of adding a cascode circuit has been conventionally and widely employed. Further, a reference voltage circuit which is capable of improving the power supply rejection ratio while operating at lower voltage has been employed (for example, see Japanese Patent Application Laid-open No. 2007-266715). FIG. 4 is a circuit diagram illustrating a conventional reference voltage circuit.
An N-channel depletion type metal oxide semiconductor (MOS) transistor 301 and an N-channel enhancement type MOS transistor 302 form an enhancement depletion (ED) type reference voltage circuit 310. An N-channel depletion type MOS transistor 303 which operates as a cascode circuit is connected in series to the ED type reference voltage circuit 310. An N-channel enhancement type MOS transistor 304 serving as a control current source is connected in parallel with the N-channel enhancement type MOS transistor 302. An N-channel depletion type MOS transistor 305 having a gate terminal and a source terminal connected to each other is connected in series to the N-channel enhancement type MOS transistor 304. Further, the source terminal of the N-channel depletion type MOS transistor 305 is connected to a gate terminal of the N-channel depletion type MOS transistor 303. The N-channel enhancement type MOS transistor 304 and the N-channel depletion type MOS transistor 305 form a bias circuit 311 for supplying a constant bias voltage to the N-channel depletion type MOS transistor 303 which operates as the cascode circuit.
In the circuit described above, in a case where characteristics and transconductance coefficients of the N-channel enhancement type MOS transistors 302 and 304, and those of the N-channel depletion type MOS transistors 303 and 305 are the same, source-backgate voltage-drain current characteristics of the respective depletion type transistors are the same, and drain currents of the respective depletion type transistors are the same. Therefore, source potentials of the respective depletion type transistors are the same.
In this case, the source potential of the N-channel depletion type MOS transistor 305 may be made lower than the source potential of the N-channel depletion type MOS transistor 303 by employing the following methods:
(1) making the transconductance coefficient of the N-channel enhancement type MOS transistor 304 larger than the transconductance coefficient of the N-channel enhancement type MOS transistor 302 by, for example, fixing L length and increasing W length;
(2) making the transconductance coefficient of the N-channel depletion type MOS transistor 305 smaller than the transconductance coefficient of the N-channel depletion type MOS transistor 303; and
(3) implementing both methods of (1) and (2) described above.
In this manner, the reference voltage circuit of FIG. 4 is capable of operating at lower voltage.
However, in the reference voltage circuit described above, current flows through two paths, which are a path from the N-channel depletion type MOS transistor 305 to the N-channel enhancement type MOS transistor 304 and a path from the N-channel depletion type MOS transistor 303 to the ED type reference voltage circuit 310. Therefore, there has been a disadvantage of high current consumption.